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AR# 65501

Vivado_Router: Vivado router fails to route a design which uses IODELAY instances to delay internal signals


Vivado Implementation fails to route my design completely. Below are some of the critical warning messages issued:

"[Route 35-54] Net: SYS_PLL_INST/inst/clk_in1_SYSTEM_PLL is not completely routed.
[Route 35-54] Net: CPU_INF_inst/IO_BUF_IF0[3].if0_iobuf_addr/O is not completely routed.
[Route 35-54] Net: CPU_INF_inst/IO_BUF_IF0[4].if0_iobuf_addr/O is not completely routed.
[Route 35-54] Net: CPU_INF_inst/IO_BUF_IF0[1].if0_iobuf_addr/O is not completely routed.
[Route 35-54] Net: CPU_INF_inst/IO_BUF_IF0[2].if0_iobuf_addr/O is not completely routed."

In my design there are nearly 200 IDELAY instances which are used to delay the internal signals. The Vivado placer failed to place these instances at correct/optimal locations, as a result of which the router fails.


The failing nets originate from an I/O port (source) and drive FF,LUT, MMCM instances (loads). In the device view of the Implemented design, examine the routing resource which needs to be taken by the failing nets.

It can be seen that the IDELAY site corresponding to the package pin to which the I/O port was locked is occupied by another idelay instance in the design, and there is no routing resource available for this failing net.

The IODELAY site is used as a route-thru to route from I/O pad to Slice, MMCM etc. The nets are failing to route as the IDELAY site is not free.

The work-around is to manually lock down the IODELAY instances to correct sites.

The following commands can be used in an Implemented design to export the current location of IDELAY instances in XDC constraint format.

set idelay_elements [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.iodelay.IDELAYE2 }];
foreach idelay $idelay_elements {
set IDELAY_loc [get_property LOC [get_cells $idelay]];
puts "set_property LOC $IDELAY_loc \[get_cells $idelay\]";

Modify the location of IDELAY instances (which are currently placed in the IODELAY sites which correspond to failing nets) to sites whose corresponding I/O pad is not used.

AR# 65501
Date 01/20/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2015.2
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