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AR# 65502

Vivado 2015.1 fails to route the design which was successful in Vivado 2014.4

Description

My design fails during BitGen with the below error in Vivado 2015.1:

ERROR: [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_cfg/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/io0_t, blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_1/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/io0_t.

Solution

Below is the output of the report_route_status command executed on the Implemented design:


Nets with Routing Errors:
  blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_1/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/io0_o
    Unrouted Pin: blackbird_system_wrapper1/spi_mem1_io0_iobuf/OBUFT/I
  blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_cfg/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/io0_o
    Unrouted Pin: blackbird_system_wrapper1/cfg_spi_io0_iobuf/OBUFT/I

The unrouted pins are the I pins of OBUFT instances. The T pin of these OBUFT instances are driven from FDRE which has conflicting constraints, i.e., IOB=FALSE and LOC=OLOGIC_XxYy. 

As a result the tool is placing these FDRE instances at the OUTFF BEL in the OLOGIC site which is incorrect.

Either of the below work-arounds can be used:

1. Change the IOB property to TRUE on the flop.

or

2. Use the below BEL constraints to lock the FDRE at the TFF BEL instead:

set_property BEL TFF [get_cells blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_cfg/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPI_TRISTATE_CONTROL_III]
set_property BEL TFF [get_cells blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_1/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPI_TRISTATE_CONTROL_III]
AR# 65502
Date Created 09/25/2015
Last Updated 01/20/2016
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite