The Spartan-6 Reliability Estimation section of PG036 requires an update for Spartan-6 SEM v3.4 and newer versions.
Sample Spartan-6 Reliability Estimation
Table 1: Example Device FIT Data for Spartan-6 FPGAs. See (UG116) for the latest data:
|Configuration Memory||179 FIT/Mb|
|Block Memory||375 FIT/Mb|
|Distributed Memory (same as Configuration Memory)||179 FIT/Mb|
The controller and shims use approximately 241 logic slices, 52 I/O blocks, and 10 block RAM (18 Kb) in a mid-sized XC6SLX45T device.
Consider the configuration bit contribution:
The controller and shims use several hundred flip-flops for data, their contribution is ignored due to the small number of bits.
The controller and shims use 61 LUT RAM. The usage breakdown is as follows:
The MON shim uses 27 LUT RAM for data buffering, but the buffers are generally empty and data corruption not observable. These memory bits are therefore ignored.
The controller uses 34 LUT RAM for data storage. Errors in used locations are highly likely to halt the controller. Approximately 512 memory bits are used.
The controller uses ten block RAM (18 Kb). The usage breakdown is:
An internal buffer uses one block RAM. In the data array, 2212 bits are allocated to data buffers used in correction and classification.
A soft error here would only cause potential issue if it occurred during mitigation activity. No permanent data resides here so these are ignored.
Another 4898 bits are allocated to constant storage. Errors in these locations are highly likely to break the controller and must be considered in the analysis. The remaining 11322 bits are unused.
The controller firmware resides in two block RAMs. The word count is approximately 1812 out of 2048, with at least 602 of the used words only executed once at system start or as a debug and are therefore ignored. The number of bits considered for the analysis is 26028.
The soft logic FRAME ECC module within the controller stores the ECC checksums in the remaining block RAM.
These block RAM contents are protected by the FRAME ECC, and do not contribute to the Block RAM Bit FIT.
As computed above, these block RAMs do contribute to the Configuration Bit FIT.
The total controller FIT is then:
8.1 FIT + 0.09 FIT + 11.1 FIT = 19.3 FIT