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AR# 6556

V2.1i COREGEN, VERILOG, VHDL: New HDL behavioral simulation flow does not generate .VHD and .V models for simulation


Keywords: coregen, hdl, verilog, vhdl, functional, behavioral, sim

Urgency: standard

General Description:
In the new 2.1i release, the CORE Generator does not directly generate
.VHD and .V models for behavioral simulation. (.VEO and .VHO templates
are generated instead).


1. The 2.1i CORE Generator does not generate a .VHD or .V
file for each core in the 2.1i release.
Instead, it creates a .VHO (for VHDL) or .VEO (for Verilog) template file
containing the code snippets required to integrate the core into a
higher level design block's behavioral simulation netlist.

2. Before any behavioral simulation of a core can be done,
you must :

- run the get_models utility to extract the models into a separate source

- analyze the library, if required by your simulator, to a library named "xilinxcorelib".
(VHDL and compiled Verilog simulators)

- set your simulator to point to the extracted (and analyzed) library

Please refer to the Design Flows chapter of the CORE Generator User Guide
(available from within the CORE Generator under Help->Online Documentation)
for more details. The latest version is accessible at:
The details are documented in the HDL Design Flows section of the last chapter.
AR# 6556
Date Created 05/18/1999
Last Updated 09/03/2001
Status Archive
Type General Article