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AR# 65607

Xilinx Platform Flash XL PROM (XCF128X) Discontinuation Guidance


The Platform Flash XL PROM (XCF128X) is a 128Mbit configuration solution that has been discontinued as of July 2015 (XCN15008).


The Platform Flash XL PROM products are manufactured by a third party FLASH manufacturer. This manufacturer reviewed its product line and chose to prune low volume products to enable improved supply chains efficiency in November 2014. 

XCF128X was one of those low volume products. Unfortunately, there were no reasonable commercial terms that could convince the manufacturer to continue support, so Xilinx is forced to discontinue the product.

This configuration solution was used with Virtex-5 and Virtex-6 FPGAs. There is no direct replacement for this solution so the last time buy (LTB) option is recommended.

Alternate solutions require board changes. This answer record provides considerations and a comparison for an alternate pin compatible solution.



The last time buy (LTB) is the recommended option and the only alternative to the Platform Flash XL solution that does not require a board change.

See XCN15008 and contact the Xilinx Sales Representative for the last time buy (LTB) through to June 01, 2016.

Alternate Solution:

The Micron PC28F128P30T family comes in a pin compatible EasyBGA64 package, but trade-offs in performance and board changes that are required are described below:

Performance Consideration:

  • The Micron PC28F128P30T does not have the same configuration time performance as the Xilinx XCF128X. The table below provides an estimation of the configuration time difference that can be expected for Virtex-6 FPGAs. Virtex-5 FPGAs have a similar configuration time difference.  The equations in the Table footnotes 3 and 4 can be used to calculate the configuration time estimates for the Virtex-5 family.

Family Device Bitstream Size (bits) Platform Flash XL Slave SelectMAP(XCF128XFTG64C, XCF128XFT64)
Micron PC28F128P30T Basic BPI Async Mode(3) x16
Micron PC28F128P30T BPI Page Async Mode(4) x16
Micron PC28F128P30T BPI Page Async Mode x16 with 10% estimated compression(2) (ms)
CCLK Tolerance Virtex-6 FMCCKTOL=55% Virtex-6 FMCCKTOL=55% Virtex-6 FMCCKTOL=55%
ConfigRate NA 3 16 (5) 16 (5)
Frequency(1) 50 MHz 1.35- 4.65MHz 7.2-24.8MHz 7.2-24.8MHz
Virtex-6 LXT XC6VLX75T 26,239,328 33 1215 256 231
Virtex-6 LXT XC6VLX130T 43,719,776 55 2024 427 384
Virtex-6 LXT XC6VLX195T 61,552,736 77 2850 601 541
Virtex-6 LXT XC6VLX240T 73,859,552 92 3419 721 649
Virtex-6 LXT XC6VLX365T 96,067,808 120 4448 938 844
Virtex-6 SXT XC6VSX315T 104,465,888 131 4836 1020 918
Virtex-6 HXT XC6VHX250T 79,862,624 100 3697 780 702
Virtex-6 HXT XC6VHX255T 79,862,624 100 3697 780 702
Virtex-6 HXT XC6VHX380T 119,784,608 150 5546 1170 1053

  1. The slowest frequency in the FMCCKTOL range is used for worst case. 
  2. The table shows an example 10% compression rate impact on the configuration time. The compression rate is design dependent. 
  3. Basic asynchronous BPI configuration time is calculated using the equation: (bitstream size/16/configuration frequency) 
  4. Page mode asynchronous BPI configuration time is calculated using the equation: (1/configuration frequency)(2+1+1+1+1+1+1+1 cycles/8 words)(1 word/16bits)(bitstream size)
  5. Bitstream will need to be regenerated when page mode is used. Ensure the software BitGen options for page mode are set: configrate 16, BPI_page_size 8, and BPI_1st_read_cycle 2.

Pin Package Compatibility Consideration:

The Platform Flash XL PROM comes in an EasyBGA 64 package and the Micron P30 family offers a pin compatible 128Mbit device, but there are some pin differences listed below:

Virtex-6/Virtex-5 FPGA Pin Name XCF128X Pin Name Micron PC28F128P30T Pin Name EasyBGA64 Pin# Requirements when migrating from XCF128XL to the Micron PC28F128P30T flash family
M[2:0] M2 pin change required if XCF128XL was used in Slave SelectMAP mode PC28F128P30T uses Master BPI mode M[2:0]=010
RDWR_B No change required
CSI_B/CS_B No change required
NC VSS H2 Change required. P30 VSS should be tied to gnd.
NC CLK E6 Change required. CLK must be tied to VSS or VCCQ.
NC ADV# F6 Change required. ADV# must be tied to VSS.
NC VCCQ D5 Change required. VCCQ should be tied for P30 to same connection as G4.
NC VCCQ D6 Change required. VCCQ should be tied for P30 to same connection as G4.
/L RFU H1 No change required
/RP RST# D4 No change required
NC WAIT F7 No change required
VSSQ VSS H4 No change required
READY_WAIT RFU B8 No change required
/WP RFU G2 No change required
A[22:0] A[23:1] No change required. Pin connections remain the same, labeling difference only (A0 on XCF128X = A1 on PC28F128P30T).
NC WP# C6 No change required. If write protection functionality is desired, review the PC28F128P30T data sheet for details on usage. /WP should be tied high if in-system programming is required.
K RFU F1 No change required. Clock is not required for asynchronous mode.
/G OE# F8 No change required. Same function different pin name.
/W WE# G8 No change required. Same function different pin name.
/E /CE B4 No change required. Same function different pin name.
AR# 65607
Date Created 10/08/2015
Last Updated 01/28/2016
Status Active
Type General Article
  • Platform Flash