Version Found: v1.0
Version Resolved: See (Xilinx Answer 58435)
For AXI enabled DDR3/DDR4 SDRAM IP designs, the data mask signals should be driven by the AXI layer of the IP based on the write strobes for Read-Modify-Write (RMW) commands.
To fix this issue, the following lines of code inside <ip_name>_ddr3.sv, instance name u_ddr3_mem_intfc:
Go to line 750:
replace it with the following:
Note: Replace "ddr3" with "ddr4" if this is a DDR4 interface.
To prevent Vivado from overwriting the IP edits, it is recommended to create your own IP Repository that contains the RTL edits.
To do this, follow the steps below:
1. Copy the DDR3/DDR4 SDRAM IP directory, for example: C:\Xilinx\Vivado\2015.3\data\ip\xilinx\ddr3_v1_0
2. Make your edits to the IP in this copied directory, and save the files anywhere.
3. Add it in the IP Catalog by clicking IP Settings=>Add a Repository, and selecting the saved location of the edited files.
10/12/2015 - Initial Release