I have a design based on a module containing 8LUT+16FF.
I specify RLOC attributes in HDL to have the BELs packed into the same CLB. In the top level, the module is called 25 times.
I then draw a pblock ranging slice_x0y0:slice_x9y4, expecting the instances to 100% fit into this region.
However, the following error occurs in place_design:
Is it a valid error and how can I work around this?
Multi-column macros in devices with irregular column spacing are difficult to support.
The placer cannot exhaustively check all potential column choices. Therefore an RLOC_ORIGIN is necessary to point the placer to a legal column placement.
It is best to avoid multi-column macros unless you want to also specify the placement location.
The work-around would be to add LOC or RLOC_ORIGIN to the instances instead of drawing the pblock.
Alternatively, modify the basic module to occupy a single slice, double the generate loop, and keep the pblock.