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AR# 65751

UltraScale+ PCI Express Integrated Block - Release Notes and Known Issue

Description

This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express Integrated Block Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Changes in v1.1 (Rev2)

 

  • Port Change
    • No mandatory port changes. Added new optional ports and interfaces for PCIe DRP, GT DRP, GT Wizard, In System IBERT, Transceiver Control and Status ports.
  • Bug Fix
    • Added soft fix for Gen1 and Gen2 to have proper de-skew between lanes.
    • Added work-around for timeout issue when link is in L0s.
    • Added work-around for GT issue where COM alignment change in between FTS transmission.
    • Added PMARESET fix, and an update to the GT reset sequence during the rate change. Added CDRHOLD fix to ensure that CDR and RX Equalization start working first and do not give any false indication that data is already good.
    • Added Sequence number FIFO fix for ES2 silicon.
  • Feature Enhancement
    • Added GT DRP, PCIe DRP and Transceiver Control and Status ports option in the core configuration GUI.
    • Added simulation model support to run post Synthesis and post implementation simulation.
    • Added support for 125 MHz and 250 MHz reference clock option.
    • Added GT Wizard support for Xilinx example design in the Shared Logic page.
    • Added System IBERT support.
  • Other
    • Moved pblock constraints from the IP level XDC file to the Xilinx example design top XDC file to allow users to access SLICE range settings in 512-bit AXIST mode
    • Revision change in one or more subcores

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v1.1 (Rev2)
2016.3
v1.1 (Rev1) 2016.2
v1.1 2016.1
v1.0 (Rev1) 2015.4
v1.0 2015.3

 

Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version
(Xilinx Answer 68112) v1.1 (Rev. 68112) 2016.3
(Xilinx Answer 68069) v1.1 (Rev. 68069) 2016.3
(Xilinx Answer 67712)
v1.1(Rev 67712) 2016.2
(Xilinx Answer 67617) v1.1 (Rev 67617) 2016.2
(Xilinx Answer 67307) v1.1(Rev 67307) 2016.1
(Xilinx Answer 67144) v1.1 (Rev 67144) 2016.1
(Xilinx Answer 65721)
v1.0 (Rev1)
2015.3

 

Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 68112) MSI-X Vector Table and PBA v1.1 (Rev2) Not Resolved Yet
(Tactical Patch Provided)
(Xilinx Answer 68069) CPLL Calibration Block Integration and MSI-X Core GUI Issue v1.1 (Rev2) Not Resolved Yet
(Tactical Patch Provided)
(Xilinx Answer 67712) Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs: v1.1 (Rev1) v1.1(Rev2)
(Xilinx Answer 67617) X16Gen3 Support for -1L and -2L devices v1.1 (Rev1) Not Resolved Yet
(Tactical Patch Provided)
(Xilinx Answer 67307) Tactical patch with various fixes v1.1 v1.1 (Rev1)
(Xilinx Answer 67307) Various Fixes
V1.1 Not Resolved Yet
(Xilinx Answer 67144) Incorrect GT Quad Location for Virtex 9P Devices v1.1 Not Resolved Yet

 

Other Information:

 

(Xilinx Answer 68134) UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express- Integrated Debugging Features and Usage Guide

Revision History:

10/22/2015 Initial release
04/13/2016 Updated for 2016.1 Release
05/14/2016 Added (Xilinx Answer 67144)
06/08/2016 Updated for 2016.2 Release
08/06/2016 Added (Xilinx Answer 67617)
08/16/2016 Added (Xilinx Answer 67712)
10/05/2016 Updated for 2016.3 Release
10/30/2016 Added (Xilinx Answer 68112)
AR# 65751
Date Created 10/20/2015
Last Updated 11/21/2016
Status Active
Type Release Notes
IP
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express