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AR# 65751

UltraScale+ PCI Express Integrated Block - Release Notes and Known Issue


This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express Integrated Block Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v1.3 (Rev3) 2018.2
v1.3 (Rev2)
v1.3 (Rev1) 2017.4
v1.3 2017.3
v1.2 (Rev1) 2017.2
v1.2 2017.1
v1.1 (Rev3) 2016.4
v1.1 (Rev2)
v1.1 (Rev1) 2016.2
v1.1 2016.1
v1.0 (Rev1) 2015.4
v1.0 2015.3


Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version
(Xilinx Answer 71191) v1.3 (Rev. 71191) 2018.1
(Xilinx Answer 70012) v1.3 (Rev. 70012) 2017.3
(Xilinx Answer 69405) v1.2 (Rev.69405) 2017.2
(Xilinx Answer 69155) v1.2 (Rev. 69155) 2017.1
(Xilinx Answer 68478) v1.1 (Rev. 68478) 2016.4
(Xilinx Answer 68310) v1.1 (Rev. 68310) 2016.3
(Xilinx Answer 68112) v1.1 (Rev. 68112) 2016.3
(Xilinx Answer 68069) v1.1 (Rev. 68069) 2016.3
(Xilinx Answer 67712) v1.1(Rev 67712) 2016.2
(Xilinx Answer 67617) v1.1 (Rev 67617) 2016.2
(Xilinx Answer 67307) v1.1(Rev 67307) 2016.1
(Xilinx Answer 67144) v1.1 (Rev 67144) 2016.1
(Xilinx Answer 65721) v1.0 (Rev1)


Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 71191) Link does not train in Gen1 design with Refclk at 125MHz & 250MHz speeds v1.3 (Rev2)
v1.3 (Rev3)
(Xilinx Answer 70952)
Consecutive reads on MSIX internal vector table can cause completion timeout in Gen3x16 configuration v1.3 (Rev2)
Not Resolved Yet
(Xilinx Answer 70012) Tactical patch for issue fixes and enhancements v1.3 v1.3(Rev1)
(Xilinx Answer 69405) Tactical patch for issue fixes and enhancements v1.2(Rev1) v1.3
(Xilinx Answer 69155) Gen3x16 support for -2L devices v1.2 v1.3(Rev1)
(Xilinx Answer 69063) Gen3x16 configuration support on Virtex UltraScale+ -2LV (0.72v) Devices v1.2 v1.3(Rev1)
(Xilinx Answer 68478) x16 Support in xczu7ev (fbv900 and ffvc1156) Devices v1.1 (Rev2) v1.2(Rev1)
(Xilinx Answer 68310) Link training failure when "System Reset Polarity" is set to "active high" v1.1(Rev2) v1.2(Rev3)
(Xilinx Answer 68112) MSI-X Vector Table and PBA v1.1 (Rev2) v1.1 (Rev3)
(Xilinx Answer 68069) CPLL Calibration Block Integration and MSI-X Core GUI Issue v1.1 (Rev2) v1.2
(Xilinx Answer 67712) Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs: v1.1 (Rev1) v1.1(Rev2)
(Xilinx Answer 67617) X16Gen3 Support for -1L and -2L devices v1.1 (Rev1) v1.3(Rev1)
(Xilinx Answer 67307) Tactical patch with various fixes v1.1 v1.1 (Rev1)
(Xilinx Answer 67307) Various Fixes
V1.1 v1.1 (Rev1)
(Xilinx Answer 67144) Incorrect GT Quad Location for Virtex 9P Devices v1.1 v1.1 (Rev1)


Other Information:


(Xilinx Answer 68134) UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide
(Xilinx Answer 69453) Hot Plug Support
(Xilinx Answer 71446) Link Up Issue with Dell 5810 Systems

Revision History:

10/22/2015 Initial Release
04/13/2016 Updated for 2016.1 Release
05/14/2016 Added (Xilinx Answer 67144)
06/08/2016 Updated for 2016.2 Release
08/06/2016 Added (Xilinx Answer 67617)
08/16/2016 Added (Xilinx Answer 67712)
10/05/2016 Updated for 2016.3 Release
10/30/2016 Added (Xilinx Answer 68112)
02/03/2017 Added (Xilinx Answer 68478)
01/24/2017 Updated for 2016.4 Release
04/05/2017 Updated for 2017.1 Release
07/05/2017 Updated for 2017.2 Release
08/14/2017 Added (Xilinx Answer 69405)
11/15/2017 Added (Xilinx Answer 70012)
02/11/2018 Updated Version Resolved section
06/12/2018 Added (Xilinx Answer 71191)
08/21/2018 Added (Xilinx Answer 71446)

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
69155 UltraScale+ PCI Express Integrated Block (Vivado 2017.1) - Gen3x16 support for -2L devices. N/A N/A

Associated Answer Records

AR# 65751
Date 08/31/2018
Status Active
Type Release Notes
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express
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