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AR# 65790

DDR4/DDR3 SDRAM IP - when using a Custom Memory part some timing parameters are not updated correctly


Version Found: v1.0

Version Resolved: See (Xilinx Answer 58435)

When using the Custom Memory part for DDR3 and DDR3 SDRAM IP the following timing parameters might not get passed down through the IP RTL properly which can impact simulation, hardware and controller efficiency results:

  • tRRD
  • tZQCS
  • tFAW


This issue only occurs when using a Custom Memory part for DDR4 and DDR3 SDRAM IP and does not affect other memory interface types.

To resolve the issue a tactical patch must be installed.

To install the patch, follow one of the methods listed below:

Method 1: (Vivado 2014.4 and later only)

a. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist).

b. Extract the contents of the ".zip" archive to a directory starting with the name AR65790.

Note: Most extraction tools will allow you to automatically create a directory with the same name as the zip file.

c. Run Vivado software tools from the original install location.

Method 2:

a. Create a separate directory containing patched files.

b. Extract the contents of the ".zip" archive to the desired patch directory location.

c. Set the MYVIVADO environment variable to point to this patch directory.

For example:

set MYVIVADO=C:\MYVIVADO\vivado-patch-AR65790\vivado\

d. Run Vivado software tools from the original install location.

Note: This tactical patch is only compatible with Vivado 2015.3 and DDR4 and DDR3 SDRAM IP v1.0.

Revision History:

10/29/2015 - Initial Release


Associated Attachments

Name File Size File Type
AR65790_Vivado_2015_3_preliminary_rev1.zip 1 MB ZIP
AR# 65790
Date Created 10/27/2015
Last Updated 11/09/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale