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AR# 65793

2014.4 - BRAM_TDP_MACRO Model Revision - Update DI and DO for parity intersperse every byte


In Vivado 2014.4, the following revision was added to BRAM_TDP_MACRO model.

-- 09/29/14 - Update DI and DO for parity intersperse every byte (CR 773917).

This causes the macro configured as a single ROM in my design to behave incorrectly.

Compared to the previous model, the output data bus connections differ in such a way as to produce an offset for data values which are larger than 8-bits.

In the case of 0x200, the output would register as 0x400.


The revision was made because the way in which the parity was mapped in the BRAM_TDP_MACRO caused it to have incorrect data where there were asymmetric (different) widths for read/write.

The mapping should be done so that the parity is interspersed every 8 bits. This should allow for any width conversion and for the proper data to be written out.

The implication of this is that the initialization data MUST change when migrating from one version of the macro to the other.

Because the parity bits are interspersed, the parity data vectors (i.e. INITP_00) must be initialized with the appropriate bits within the data vector.

AR# 65793
Date Created 10/27/2015
Last Updated 06/30/2016
Status Active
Type General Article
  • Vivado Design Suite - 2014.4