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AR# 65796

Vivado DRC - The DRC message for Violation PLCK-12 does not specify the objects that cause the violation.


The DRC GUI report gives a (PLCK-12) warning.

The message given in the "Details" tab in the "Violation Properties" window of this violation is similar to the following:

Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.

There is no information about the object names that are causing the violation.

How can I tell which cells are involved in the issue?


The message given in the GUI DRC report does not provide enough detail.

More details can be found in the DRC report, including the cell names.

You can generate the text DRC report by leaving the location and the file name in the "Output file" blank when you run "Report DRC...":

AR# 65796
Date 11/05/2015
Status Active
Type General Article
  • Vivado Design Suite
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