We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65800

LogiCORE IP Video Processing Subsystem v1.0 - Example design fails to meet timing inside the IP


I am trying to use the example design that comes with the Video Processing Subsystem IP, but I am getting timing errors (and the associated critical warning):

Slack (VIOLATED) : -0.105ns (required time - arrival time)

Source: design_synth_i/v_proc_ss_0/inst/v_hscaler/inst/v_hscaler_AXIvideo2MultiPixStream86_U0/j_i_i_reg_280_reg[1]/C

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.


This is a known issue in the 2015.3 release which will be resolved in a future release.

AR# 65800
Date Created 10/28/2015
Last Updated 11/02/2015
Status Active
Type General Article
  • Video Scaler