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AR# 65831

UltraScale FPGA Gen3 Integrated Block for PCI Express v4.1 (Vivado 2015.3) / AXI Bridge for PCI Express Gen3 v2.0 (Vivado 2015.3) - GT DRP Ports disabled when Falling Edge Receiver Detect is selected

Description

Version Found: 4.1

Version Resolved and other Known Issues: (Xilinx Answer 57945)

When the 'Receiver Detect - Falling Edge' option is selected in the UltraScale FPGA Gen3 Integrated Block for PCI Express /AXI Bridge for PCI Express Gen3 core generation GUI, GT DRP ports should be enabled in the GT Wizard.

However, they are currently disabled.


_________________________________________________
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in a future release of the core.

To enable GT DRP ports in Vivado 2015.3, please install the attached patches as described below.

There are two patches provided in this answer record.

For UltraScale FPGA Gen3 Integrated Block for PCI Express, please install AR65831_Vivado_2015_3_preliminary_Ultrascale_Gen3_rev1.zip.

For AXI Bridge for PCI Express Gen3, both patches must be installed.

  • The patches are for Vivado 2015.3
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2015.3 and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Repository Manager and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the core should indicate:

  • 4.1 (Rev. 65831) for UltraScale FPGA Gen3 Integrated Block for PCI Express
  • 2.0 (Rev. 65831) for AXI Bridge for PCI Express Gen3

Note: "Version Found" refers to the version where the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

11/05/2015 - Initial Release

Attachments

Associated Attachments

AR# 65831
Date Created 11/03/2015
Last Updated 11/16/2015
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
  • AXI PCIe Gen3