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AR# 65907

MIG UltraScale DDR4/DDR3 - (UG583) Package delay(P0) calculation ambiguity for differential signals

Description

Version Found: MIG v1.0

Version Resolved: See (Xilinx Answer 58435)

All skew constraints tables include a note next to differential pair matching and a foot note stating "Do not consider package delay (P0) in skew calculation".

Also there is another "important" note which states that package delay must be taken into account.

Which is correct and why there is a difference for a small number of signals?

Solution

The User Guide notes are intended to convey that package delay does not have to be included when trace matching a single differential pair. (DQS_P, DQS_N and CK_P, CK_N)

The package skew on differential pairs is already accounted for when we defined the matching constraint.

(UG583) will be modified to reflect this more clearly.


Revision History:

11/5/15 - Initial Release

AR# 65907
Date Created 11/05/2015
Last Updated 11/10/2015
Status Active
Type Known Issues
Devices
  • Virtex UltraScale
  • Kintex UltraScale
IP
  • MIG
  • MIG UltraScale