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AR# 65947

LogiCORE Tri Mode Ethernet MAC v9.0 (Rev 3) - UltraScale Plus Devices - GMII/RGMII - Timing not met on I/O Interface


When using the Tri-mode Ethernet MAC core (v9.0 rev 3) in Vivado 2015.4 to target an UltraScale Plus device with a GMII/RGMII interface, the constraints on the I/O paths are not completely met and you might see Setup/Hold violations on these paths.

This is similar to what has been seen for UltraScale devices in previous releases. (See (Xilinx Answer 60198))


To get timing closure for these I/O constraints, you will need to LOC down the package pins and the clocking elements to be in the same clock-region.

Attached to this Answer Record are LOC constraints examples for a few Kintex and Zynq US+ devices, for both GMII and RGMII mode.


Associated Attachments

Name File Size File Type
gmii_locs.txt 8 KB TXT
rgmii_locs.txt 5 KB TXT
AR# 65947
Date Created 11/11/2015
Last Updated 11/24/2015
Status Active
Type General Article
  • Kintex UltraScale+
  • Virtex UltraScale+
  • Vivado Design Suite - 2015.4
  • Tri-Mode Ethernet MAC