When using the Tri-mode Ethernet MAC core (v9.0 rev 3) in Vivado 2015.4 to target an UltraScale Plus device with a GMII/RGMII interface, the constraints on the I/O paths are not completely met and you might see Setup/Hold violations on these paths.
This is similar to what has been seen for UltraScale devices in previous releases. (See (Xilinx Answer 60198))
To get timing closure for these I/O constraints, you will need to LOC down the package pins and the clocking elements to be in the same clock-region.
Attached to this Answer Record are LOC constraints examples for a few Kintex and Zynq US+ devices, for both GMII and RGMII mode.