UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65957

UltraScale System Monitor: SYSMON I2C_SCL and I2C_SDA always connected to the SYSMON

Description

The output of the IOB in the I2C_SCLK and I2C_SDA sites are always connected to the SYSMON.

This is the case even when I set I2C_EN (Configuration register 0X43, bit 7) to 0 to disable the interface post configuration.

Depending on the usage of these pins, there is a chance that the I2C ports of the SYSMON could unintentionally be written to by the user.

What steps can be taken to ensure that this does not affect the system?

Solution

The I2C clock and data I/Os are dual purpose I/Os.

The output of these IOB will always be connected to the I2C_SDA and I2C_SCLK ports of the SYSMON.

This means that whatever is on these I/Os will be broadcast to the SYSMON. 


The following are the main cases where this can cause issues in the system:


I2C pins as user I/O:

The first scenario is when the I2C port is not being used and the I2C_SDA and I2C_SCLK ports are used as user I/O in the design. Transitions on these IOs could be interpreted as valid I2C transfers.

Transitions can either be external signals driving the I/O or output drivers in the user design driving the pin.

It is extremely unlikely that this will happen, as a number of things have to occur for a write to happen. 


The I2C slave in the SYSMON needs to see a start condition, a command and a valid address for a transfer to happen.

The start condition is a falling edge on the data line while the SCLK line is held high. 


The address is 7 bits wide and the DRP command is 32 bits wide. Not every combination of the 32 bits is a valid command for the DRP port.

This means that the chances of seeing unintended writes to the DRP port of the SYSMON are very remote.

If you do see strange behavior from the SYSMON and suspect that this is the root cause, you can monitor the JTAGMODIFIED signal to identify if a write has occurred. 


I2C Port retained for use by the FPGA design post configuration:

The other scenario that can occur is when you have an I2C slave in the fabric for communication with the I2C bus in the system.

So before configuration, the I2C is used to control the SYSMON, but afterwards the SYSMON is no longer intended to be used( I2C_EN = 0) and subsequent I2C transactions are intended for the fabric design.

If the device retains the same address on the bus then the SYSMON will also be listening.

The solution here is to Set the I2C address override bit I2C_OR(bit 15 in config register 0x43) and change the 7 bit address to one that is not used in the system.

AR# 65957
Date Created 11/12/2015
Last Updated 01/05/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale