Version Found: 2015.3
The TX_GATING attribute combined with the TBYTE_IN pin controls the bring up of the TX Bitslices.
If the TX_GATING attribute is set to FALSE, channels can become mis-aligned. This affects TX or bidirectional designs.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
To work around this issue, set the TX_GATING Attribute to ENABLE.
This can be done using the following constraint in the XDC file (note that the hierarchy will need to be changed to the specific user set-up):
The approach above will not take effect in a behavioral simulation. If this is an issue, the following approach can be used:
Update the HDL file in the following location using the flow described in (Xilinx Answer 57546):
If necessary, the edited IP can be packaged up and re-used. For more information see (UG1118).