On the dual purpose pins that can act as I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 pins for the SYSMONE1 and/or PCIE hard blocks, a 3.3v interface might see a reduction of the maximum "high" voltage to a 2.5V - 2.7V, instead of being allowed to reach the expected 3.3V VCCO level when the bank 65 is operated at VCCO_65=3.3V.
When these I/O are used for their dedicated I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 function, Vivado 2015.3 or earlier will incorrectly enable a circuit path connecting the I/O to internal low voltage circuits.
If the I/O is externally connected to 3.3V signaling levels it will result in the external signal not reaching the full logic high voltage level of 3.3V.
How do I identify whether a design is affected?
For a design to potentially be affected, the design must have all of these attributes:
What are the work-around options?
The issue is resolved in Vivado 2015.4 and newer. You can rebuild the design in Vivado 2015.4, or at a minimum, you can use Vivado 2015.4 to write a new bitstream from a design checkpoint (.DCP) file from a prior version of Vivado.
The following Tcl commands can be used to update a design without completely re-implementing the project:
The top_routed.dcp in these commands is the routed design checkpoint file from the last implementation directory of a Vivado <project> tree: <project>/*.runs/impl.*/
What designs are NOT impacted?
For more details, please see the Xilinx Customer Notice on this issue: