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AR# 66013

UltraScale – Component Mode IDELAY and ODELAY Accuracy and Resolution details



In the UltraScale/UltraScale+ datasheets, the IDELAY_RESOLUTION/ODELAY_RESOLUTION value of the IDELAY3/ODELAY3 component is defined as 2.5 to 15 ps. This is the resolution over PVT, it is not dependent on the REFCLK of the IDELAYCTRL.


An IDELAYCTRL is not required if the Delays are used in COUNT mode. IDELAYCTRL REFCLK needs to be in the range 200-800MHz as specified in the data sheet.

There is no dependency on the REFCLK speed and the interface speed of the logic (IDDR/ISERDES/ODDR/OSERDES).

If you encounter a DRC warning that the REFCLK pin should be driven by the same clock net as the associated ISERDES, this can safely be ignored.

This is part of the Component Mode Known Issues list. For updates on changes to the documentation or Vivado please refer to (Xilinx Answer 66012)


Calculating Tap Size

You can determine the current Tap size by reading the CNTVALUEOUT of the IDELAY or ODELAY when using DELAY_FORMAT = TIME, however you must account for the align delay** that is included on the RX side whenever an IDELAYCTRL is used.

Align Delay** = the difference between the Data and Clock paths to the ISERDES/IDDR/IFD/RX_BITSLICE, which will include the intrinsic delay***. 

During the calibration the IDELAYCTRL / BITSLICE_CONTROL will measure the Alignment Delay. You can measure the clock alignment by having a DELAY_VALUE = 0 during calibration (i.e. IDELAYCTRL is reset) and reading out the resulting CNTVALUEOUT. 

The alignment delay will typically be between 50 and 60 Taps with an average of 54 Taps.

If you are calculating the Tap size, remove the clock alignment portion of the delay.

For example:

DELAY_VALUE = 500ps and CNTVALUEOUT = 154.

Tap size = 500 / (154-54) = 5ps

If you are reading a value out of CNTVALUEOUT that does not make sense, please check the reset sequence as this is the most likely issue. 

See (Xilinx Answer 64198) - UltraScale I/O components reset procedure.


If the DELAY_FORMAT= TIME with a FIXED delay and EN_VTC is high then then that DELAY_VALUE will be calculated according to the resolution of the taps of the device. 

The BITSLICE_CONTROL/IDELAYCTRL will calculate the required number of taps after measuring the tap delay. If EN_VTC is low then the delay will not be compensated for V and T, increasing or decreasing the number of Taps used to build the required TIME.

If the DELAY_FORMAT= COUNT then the delay is not calibrated for V and T and no IDELAYCTRL is required, however the total delay will vary by the amount of taps used multiplied by the resolution. 

Note: As described above the Tap size can vary between 2.5 to 15 ps across PVT independent of the REFCLK.

In previous families the delay of one tap in a delay line was determined by the applied REFCLK to the IDELAYCTRL component. 


If the DELAY_TYPE is VAR_LOAD and using TIME mode, then because the TAP size varies over VT you will need to read the CNTVALUEOUT to calculate the current TAP size and use this to calculate how many TAPs are required for the new delay.

To calculate what the CNTVALUEIN should be, use the following procedure:

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:
    1. De-assert EN_VTC. Wait 10 CLKDIV cycles.
    3. Load CNTVALUEIN = ((CNTVALUEOUT -54) * (DLY1/DLY0))+54
              For example, DLY0 = 500 and CNTVALEUOUT= 154
              The new required DLY1 = 520
              CNTVALUEIN = ((154-54)*(520/500))+54 = 158
    4. Wait 10 CLKDIV cycles. Re-assert EN_VTC


When using the CNTVALUEIN port on the I/ODELAY, a maximum adjustment of 8 taps only is permitted or the signal could glitch. 

This issue applies to the Native and Component mode use of either the IDELAY or ODELAY, independent of the DELAY_FORMAT.


For faster updates, you can use DELAY_FORMAT = COUNT when IDELAYCTRL is not needed and EN_VTC can be kept Low.

The following sequence will allow for the fastest updates:

  1. Set CNTVALUEIN[8:0] = New value
  2. Set LOAD = High
  3. New delay value will be loaded and CNTVALUEOUT[8:0] = new value. 1 clock cycle later, the new delay value will be used.
    As the delay line updates to the new delay value, a glitch might be possible when input data is changing.
    For glitchless adjustments, limit the delay adjustments to 8 taps.
  4. (Option for multiple updates) Go to step 3 for multiple delay adjustments.
    Please note that adjustments to CNTVALUEIN are possible every clock cycle (CLK), but the delays will take effect the next clock cycle after CNTVALUEOUT has been updated.
  5. Set LOAD = Low to ensure delay line will not update



The delay line has a minimum of 512taps*2.5ps = 1280ps. The Maximum is 512taps*15ps = 7.68ns.

Cascading can be used to achieve delays greater than 1.25ns. If using cascading to achieve a DELAY > 1.25ns with a DELAY_FORMAT = TIME, delays in the same site must have an equal delay.

For example, for a 1.5ns delay the split should be 0.75 in the IDELAY and 0.75 in the ODELAY.

If a CASCADE of IDELAY-ODELAY is used in VAR_LOAD mode, the values will need to be entered for both components separately. 

The sequence detailed above must be done for the IDELAY and also for the ODELAY. The TAP size for IDELAY/ODELAY and in a MASTER/SLAVE pair are comparable.


Intrinsic Delay*** = the delay through the IDELAY/ODELAY when DELAY_VALUE = 0, and can be viewed in a Timing Report. 

The Timing Report does not model the Align Delay. 

Note: The alignment delay is not included in simulation. If you simulate a component mode IDELAY with DELAY_VALUE = 0, the CNTVALUEOUT will be 0. 

If you simulate a native mode IDELAY, for example RX_BITSLICE, or RXTX_BITSLICE with DELAY_VALUE = 0, the CNTVALUEOUT will be 8. 

The 8 taps model the intrinsic delay of the IDELAY, not the alignment delay.

Note: There is no dependency on the REFCLK speed and the interface speed of the logic (IDDR/ISERDES/ODDR/OSERDES). 

If you encounter a DRC warning that the REFCLK pin should be driven by the same clock net as the associated ISERDES, this can safely be ignored.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66012 UltraScale/UltraScale+ - Known issues list when using component mode for I/O interfaces i.e IODELAY / IOSERDES. N/A N/A
AR# 66013
Date 01/09/2018
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
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  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
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