If the REFCLK to the IDELAYCTRL is slower than the serial data interface, then errors can be seen in the received data.
Specifically in VAR_LOAD or Variable mode, the delay line might not get incremented if the IDELAYCTRL clock is not the same frequency or higher than the high speed serial clock.
**Note the IDELAYCTRL is only required when the delays are in TIME mode, if COUNT mode is used then no IDELAYCTRLs are required. For interfaces with a mix of TIME and COUNT mode then any bank with TIME Mode delays will require a IDELAYCTRL.
This is part of the Component Mode Known Issues list. For updates on changes to the documentation or Vivado please refer to (Xilinx Answer 66012)
In previous families the delay of one tap in a delay line was determined by the applied REFCLK to the IDELAYCTRL component. For example, the REFCLK at 200MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
In UltraScale there is still a REFCLK requirement and this is given in the SelectIO User Guide (UG571): http://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug571-ultrascale-selectio.pdf
The REFCLK frequency is listed as a range of 200 to 800 MHz and this attribute should be set to match the actual frequency of the clock connected to the REFCLK port.
There is no dependency on the REFCLK speed and the interface speed of the logic (IDDR/ISERDES/ODDR/OSERDES).
If you encounter a DRC warning that the REFCLK pin should be driven by the same clock net as the associated ISERDES, this can safely be ignored.
Note: In a bank if there are no DELAYs using DELAY_FORMAT = TIME then there is no need to include an IDELAYCTRL for that bank.