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AR# 66022

Zynq-7000 AP SoC, DDR - What is the correct ordering for the PS DDR read gate training results?

Description

Version 1.10 of the Zynq-7000 TRM cites that the read FIFO training is as follows, but many of these registers do not exist.

What is the correct ordering?

The fifo_we_slave ratios for each slice(0 through 3) must be interpreted by software in the following way:
Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]}
Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]}
Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]}
Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}

Solution

The correct ordering is as follows:

The fifo_we_slave ratios for each slice(0 through 3) must be interpreted in the following way:
Slice0: fifo_we_ratio_slice_0[10:0] = {reg69_6a1[9],reg69_6a0[18:9]}
Slice1: fifo_we_ratio_slice_1[10:0] = {reg6c_6d2[10:9],reg69_6a1[18:10]}
Slice2: fifo_we_ratio_slice_2[10:0] = {reg6c_6d3[11:9],reg6c_6d2[18:11]}
Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,reg6c_6d3[18:12]}

AR# 66022
Date Created 11/19/2015
Last Updated 11/20/2015
Status Active
Type General Article
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q