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AR# 66029

LogiCORE IP JESD204 PHY v3.0 - Core fails to generate UltraScale Transceiver with correct settings for some configurations


When generating a JESD204 PHY in Vivado 2015.3 with more than 4 lanes and where the "Starting Transceiver Location" parameter is not set at a QUAD boundary, the UltraScale Transceiver IP will be incorrectly generated.

The reason for this error is the JESD204 PHY IP is attempting to set the source of the reference clock to an incorrect location. The Vivado Tcl console reports the following error:

ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

Designs that have the "Starting Transceiver Location" parameter set to a QUAD boundary or use 4 or less lanes are not affected by this issue.


The JESD204 PHY needs to be re-generated and the starting point of the transceiver channel needs to be at a QUAD boundary.

The UltraScale Transceiver can then be placed into the correct location by setting the channels in the constraint file of the design.

An example of setting the location constraints can be seen below.

set_property LOC GTH3_CHANNEL_X0Y0[get_cells i_<core_name>_support_block/i_gtwizard_top/core_gt_i/inst/gen_gtwizard_gthe3_top.<core_name>_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST]

set_property LOC GTHE3_CHANNEL_X0Y1 [get_cells i_<core_name>_support_block/i_gtwizard_top/core_gt_i/inst/gen_gtwizard_gthe3_top.<core_name>_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST]

AR# 66029
Date 11/30/2015
Status Active
Type General Article
  • JESD204