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AR# 66052

LogiCORE 1G/2.5G Ethernet PCS/PMA or SGMII v15.1 or earlier - Synchronous SGMII over LVDS - UltraScale - SGMII calibration routine does not have sufficient max delay in a single IDELAY

Description

The SGMII calibration routine does not have sufficient max delay in a single IDELAY in the IP, as the delays in the delay chain are insufficient to find two edges of a 625MHz clock.

Solution

Because the delays in the delay chain are insufficient to find two edges of a 625MHz clock, you will have to cascade an IDELAY and an ODELAY component.

An additional ODELAY component is added to the existing idelay_cal delay chain.

The count value generated in the logic is fed to both the IDELAY and ODELAY and the final value given to the logic is multiplied by 2 in order to compensate for the cascading of 2 delay elements.


Please use the attached file to replace the one in the IP. You can compare the attached file with the version in the IP to see the differences.

This is applicable for all releases of Synchronous SGMII over LVDS for UltraScale, and will be included in the 2016.1 release.

Attachments

Associated Attachments

Name File Size File Type
gig_ethernet_pcs_pma_1_serdes_1_to_10_ser8.v 14 KB V
AR# 66052
Date Created 11/25/2015
Last Updated 11/30/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.4
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII