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AR# 66054

UltraScale Memory IP - What is the appropriate way to create a VIO reset for the provided Example Design?

Description

When debugging hardware issues, it is useful to have a VIO reset to ease ILA triggering and debug usage of the Advanced Traffic Generator.  

This answer record provides steps to create a VIO reset.

Solution

1. In order to arm a trigger during reset, the VIO reset must be clocked from a free running clock.

It cannot be clocked by any of the Memory IP MMCM output clocks.

The following is a sample rtl:

input                   CLK_FPGA_P,
input                   CLK_FPGA_N

  wire        vio_clk_int;
  wire        vio_clk;

IBUFDS init_clk_in (
   .I   (CLK_FPGA_P),
   .IB  (CLK_FPGA_N),
   .O   (vio_clk_int)
 );

  BUFGCE_DIV #(
     .BUFGCE_DIVIDE(2),      // 1-8
     // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
     .IS_CE_INVERTED(1'b0),  // Optional inversion for CE
     .IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
     .IS_I_INVERTED(1'b0)    // Optional inversion for I
  )
  BUFGCE_DIV_inst (
     .O(vio_clk),     // 1-bit output: Buffer
     .CE(1'b1),   // 1-bit input: Buffer enable
     .CLR(1'b0), // 1-bit input: Asynchronous clear
     .I(vio_clk_int)      // 1-bit input: Buffer
  );

2. The failing edge from the VIO reset then generates a pulse for the MIG IP reset. 

The following is a sample rtl:

  wire       vio_sys_rst;
  reg        vio_sys_rst_z1 = 0, vio_sys_rst_z2 = 0, vio_sys_rst_pulse = 0;

 vio_0 u_vio (
    .clk (vio_clk),
    .probe_out0 (vio_sys_rst)
    );
   
always@(posedge vio_clk) begin
        vio_sys_rst_z1            <= vio_sys_rst;
        vio_sys_rst_z2            <= vio_sys_rst_z1;
        vio_sys_rst_pulse      <= (!vio_sys_rst_z1 && vio_sys_rst_z2);
end


ddr4_0 u_ddr4_0
  (
   .sys_rst           (vio_sys_rst_pulse),
   ..
   ..
   ..

3. Ideally the VIO and dbg_hub should be clocked using the same free running clock.  

The following XDC constraint can be used:

connect_debug_port dbg_hub/clk [get_nets clk]

4. In order to avoid false timing violations on an async cross clocked reset, a false path constraint is required.  

The following XDC constraint can be used:

set_false_path -to [get_pins -hierarchical -filter {NAME =~ *infrastructure/rst*_sync_r*/PRE}]

AR# 66054
Date Created 11/25/2015
Last Updated 11/30/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale