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AR# 66086

Vivado - Routing errors due to invalid BUFG load splitting

Description

I have a successfully routed Vivado 2015.2 design. However when the design is migrated to Vivado 2015.3, it has the following routing errors:

 

Nets with Routing Errors:
  IBUFDS_MgtRefClk_148_35_n_5
    Conflicting Routing Nodes -- only the first 10 are listed, use -show_all to get the full list:
      CLK_HROW_TOP_R_X95Y182/CLK_HROW_CK_BUFHCLK_L7
      CLK_HROW_TOP_R_X95Y182/CLK_HROW_CK_HCLK_OUT_L7 (BUFHCE_X0Y43/O)
      CLK_HROW_TOP_R_X95Y182/CLK_HROW_CK_MUX_OUT_L7 (BUFHCE_X0Y43/I)
      INT_R_X39Y164/FAN_ALT2
      INT_R_X39Y164/FAN_ALT5
      INT_R_X39Y164/FAN_BOUNCE2
      INT_R_X39Y164/FAN_BOUNCE5
      INT_R_X39Y166/FAN_ALT2
      INT_R_X39Y166/FAN_ALT5
      INT_R_X39Y166/FAN_BOUNCE2

 

Why is this happening?

Solution

In the error message above, a change in opt_design causes the routing issue. opt_design is moving a IBUFDS_GTE2 -> BUFG -> LUT connection to a IBUFDS_GTE2 -> LUT connection.

This change causes a new BUFHCE global clock resource to be used, but not counted as the IBUFDS_GTE2 -> LUT connection is not a global clock.

This fails routing instead of failing in place_design.

To work around this issue, the following parameter can be set:

set_param logicopt.enableSplitBUFGNonSeqLoads 0

Alternatively, a DONT_TOUCH constraint can be used on the affected nets.

This issue has been resolved for the 2016.1 version of Vivado.

AR# 66086
Date Created 12/02/2015
Last Updated 01/20/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.3