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AR# 66140

MIG 7 series (LPDDR2) - Incorrect width of app_wdf_mask signal seen in instantiation template and top level file


Version Found: MIG 7 Series v2.4 Rev1

Version Resolved: See (Xilinx Answer 54025)

When I generate 7 series MIG for a 32 bit wide LPDDR2 component, the instantiation template and mig_7series_0.v generated with MIG IP shows an incorrect width of 19 bits for app_wdf_mask signal.

Due to this incorrect width in mig_7series_0.v file, the below warning is issued during synthesis of the MIG example design.

[Synth 8-689] width (16) of port connection 'app_wdf_mask' does not match port width (19) of module 'mig_7series_0' [..example_top.v":377]


The width of the app_wdf_mask signal should be 16 bit for a 128 bit wide app_wdf_data signal.

You can copy the below definition and can connect the 16bit input signal to app_wdf_mask and safely ignore the warning message.

input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1:0] app_wdf_mask,

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 66140
Date Created 12/06/2015
Last Updated 12/23/2015
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2015.4
  • MIG 7 Series