Version Found: 2015.3
When using the High Speed I/O Wizard for receive or bidirectional interfaces, the bit slice FIFOs must be enabled together to allow all of the bit slice output data to be aligned.
The High Speed I/O Wizard initially assumes each bit slice will be independent, and consequently each FIFO_RD_EN is handled separately. However this can cause the individual bit slices to read at different times, causing the interface to become mis-aligned.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed Select IO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
To work around this issue, two changes are required.
First, you will need to create a single FIFO_RD_EN for the whole interface to ensure that all FIFOs are read on the same edge.
The core should be used as is and the FIFO_RD_EN logic as shown below should be added externally to the core.
The FIFO_EMPTY furthest from the CLKIN to the source synchronous interface should then be used to drive all of the FIFO_RD_EN's of the interface.
In the diagram below, Bit slice 51 is the furthest from the Clock and so FIFO_EMPTY is used for the FIFO_RD_EN.
Second, in rx_bs.v which is located here ..
The fifo_empty ports are not consistently declared as output ports:
If necessary, the edited IP can be packaged up and re-used. For more information see (UG1118).