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AR# 66149

UltraScale Memory IP - UltraScale KU095/VU095 Memory pin out recommendations

Description

The UltraScale devices XCKU095 and XCVU095 have only one clock region between two I/O columns in the center of the device which might require special pin out considerations. Other devices in the UltraScale and UltraScale+ families do not require special pin out considerations since they have two or more clock regions between I/O columns. During implementation, a large proportion of the user logic needs to be placed in the center of the device for connectivity and timing reasons. 

The reduced space between the I/O columns in conjunction with the presence of several memory interface IPs, or any large high performance I/O modules, can increase the placement complexity and challenge routing resources. Following the guidelines in this document will ensure the most efficient use of available routing resources for faster and predictable timing closure.


For architectural and performance reasons, the memory interface logic needs to be placed in the clock regions located on the right hand side of the I/Os. The memory interface controller logic is usually placed next to the Addr/Cmd I/Os. A high overall device utilization or user floorplanning constraints in the area next to the Addr/Cmd I/Os can result in reduced available routing resources. When placing two memory interface IPs side-by-side with the Addr/Cmd I/Os located on the same clock region row, several adjacent clock regions become highly utilized which limits the amount of user logic that can cross over or be placed in the same area. When vertically shifted by one or more I/O banks, the potential placement and routing challenges become less prevalent.


Pin planning of memory interfaces can help reduce the possible routing congestion. Migration to 2015.3 or later version of memory IP will help with timing closure due to updates to the IP clocking and constraints. The next section discusses pin out options for different packages that will result in the most efficient use of available routing resources.


Note: Additional design and constraints recommendations are provided at the end of this document.

Solution

Memory Interface Pin Placement

The UltraScale XCKU095 device is available in four different packages and the XCVU095 device is available in six different packages. XCVU095 in packages FFVD1517 and FFVC2104 do not require special pin placement because these devices have only one I/O column in the center of the device. 

Pin placement recommendations to reduce routing challenges for all of the available packages are listed in this section. The maximum number of possible 72-bit DDR4 memory interfaces in each package is used to illustrate the pin placement recommendations. 

This is just an example, the goal is to offset the memory interfaces or at the very least offset the Addr/Cmd I/O banks. The double headed arrow represents the routing channel that is created by offsetting the Addr/cmd banks.


XCKU095 FFVA1156 Package

For XCKU095 in the FFVA1156 package a pin placement recommendation for two 72-bit DDR4 memory interfaces is shown in Figure 1. 

The placement of Address/Command Banks in horizontally adjacent interfaces A and B is offset by two clock regions to create a routing channel represented by the double headed arrow.

Figure 1: XCKU095 FFVA1156 package example pin placement


XCKU095 and XCVU095 in the FFVC1517 Package

Both XCKU095 and XCVU095 are available in the FFVC1517 package. A pin placement recommendation for two 72-bit DDR4 memory interfaces is shown in Figure 2. 

The placement of Address/Command Banks in horizontally adjacent interfaces A and B is offset by two clock regions to create a routing channel represented by the double headed arrow.

Figure 2: FFVC1517 package example pin placement

XCKU095 and XCVU095 in the FFVB1760 Package

Both XCKU095 and XCVU095 are available in the FFVB1760 package. A recommended pin placement with three 72-bit DDR4 memory interfaces is shown in Figure 3. 

For this package, memory interface A is placed with the ADDr/Cmd bank at the top to leverage the unbonded banks in the second column. Interface B and C are offset from each other which creates three routing channels between the two sides of the device.

Figure 3: FFVB1760 package pin placement


XCVU095 FFVA2104 Package

For XCVU095 in the FFVA2104 package a recommended pin placement with four 72-bit DDR4 memory interfaces is shown in Figure 4. The strategy for this package was to create a two bank routing channel in the middle of the device. 

This limits the interfaces to a one bank separation with the horizontally adjacent memory interfaces.

Figure 4: XCVU095 FFVA2104 package pin placement


XCKU095 and XCVU095 in the FFVB2104 Package

Both XCKU095 and XCVU095 are available in the FFVB2104 package. A recommended pin placement with four 72-bit DDR4 memory interfaces is shown in Figure 5. The strategy for this package was to create a two bank routing channel in the middle of the device. 

This limits the interfaces to a one bank separation with the horizontally adjacent memory interfaces.

Figure 5: FFVB2104 package pin placement

Additional recommendations

1. Migrate to 2015.3 or later version of Vivado:

a. Take advantage of the QoR improvements from newer releases

b. Upgrade the memory interface IPs to benefit from clocking and constraints improvements

2. Offset the placement of Address/Command Banks in horizontally adjacent interfaces by at least one clock region to reduce chances of routing congestion. 

The placement of the Address/Command Bank within a 72-bit 3-Bank interface depends on whether it is a DIMM or component interface. For a component interface the recommendation is to place the Address/Command Bank on the outer Banks as shown in Figure 5 for Memory Interface B. This placement enables optimal component placement with fly-by topology as shown in Figure 6.

For a DIMM interface it is recommended to place the Address/Command Bank in the center as shown in Figure 5 for Memory Interface C. This placement enables better PCB routing from the FPGA to the DIMM socket as shown in Figure 7.

Figure 6: Address/Command placement recommendation for 5 components with Fly-by topology

Figure 7: Address/Command Bank placement recommendation for DIMM

3. Avoid high device utilization, especially for LUTs as they need space to be spread out in case of high density placement

4. Design top-level connectivity to minimize crossings over memory interface IPs

5. Force spreading of memory interface logic placement to a wider area by using pblock constraints

a. By default, memory interface logic is only placed in the clock regions that include the I/O columns

b. Use two clock region wide pblock for memory interface IPs located on the right I/O columns

c. Do not apply this technique the memory interface IPs located on the left I/O columns

Example: a VU095 design with four memory interface IPs. 

Only two of them can have their placement relaxed in case of congestion: Memory Interface2 and Memory Interface3.

Figure 8: Relaxing Memory Interface placement with pblock constraints

The corresponding constraints are the following:

create_pblock MemoryInterface2_pblock
resize_pblock MemoryInterface2_pblock -add CLOCKREGION_X3Y1:CLOCKREGION_X4Y3
add_cells_to_pblock MemoryInterface2_pblock [get_cells a/b/mig_2]

create_pblock MemoryInterface3_pblock
resize_pblock MemoryInterface3_pblock -add CLOCKREGION_X3Y5:CLOCKREGION_X4Y7
add_cells_to_pblock MemoryInterface3_pblock [get_cells a/b/mig_3]

6. When migrating ensure banks selected in one device exist in the target device. Refer to the chapter Migration between UltraScale Devices and Packages in (UG583).

AR# 66149
Date Created 12/07/2015
Last Updated 01/18/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale