Version Found: 2015.3
Currently the PLL compensation is set to AUTO however it should be set to INTERNAL.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
There are two work-arounds for this issue. The first is to apply the following XDC constraint targeting the users High Speed Select IO Wizard instance.
Note that this needs to be applied to all PLLs within clk_scheme.v:
Note when using the approach above (XDC Constraints) this will not take affect in a behavioral simulation. If this is an issue the following approach can be used:
Edit the source file located in the IP directory <path_of_the_core_in_the_design>\ABCD.srcs\sources_1\ip\high_speed_selectio_wiz_0\hdl\clk_scheme.v and change the compensation from the following:
Change it to the following:
When making these edits the user should use the flow described in (Xilinx Answer 57546)
If needed, the edited IP can be packaged up and re-used. For more information see (UG1118).