The PS DDR in Zynq UltraScale+ is able to support most JEDEC configurations.
What are the limitations?
Table 17-1 of UG1085 Zynq UltraScale+ Technical Reference Guide lists the limitations of the DRAM and topologies that are supported.
Also see (DS925) Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics for maximum speeds, and (UG583) UltraScale Architecture PCB Design for PCB requirements.
Additional limitations for LPDDR4:
These will be added to v1.6 of (UG1085).