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AR# 66193

Zynq UltraScale+ MPSoC - What are the limitations of the PS DDR controller? Which device should I choose?

Description

Generally, the PS DDR in Zynq Ultrascale+ is able to accomidate all JEDEC configurations.


Solution

The PS DDR has the following limitations:

  • Maximum of 2 ranks
  • Minimum datawidth of 32-bits
  • Maximum LPDDR4 datawidth of 32-bits data + ECC
  • Maximum DDR3/DDR4/LPDDR3 datawidth of 64-bits + ECC

Using multiple ranks, DIMMs, and ECC may have reduced maximum clock rates.

This information will be eventually added to the Zynq Ultrascale+ Technical Reference Guide and Datasheets.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66194 Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
66194 Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller N/A N/A
AR# 66193
Date Created 12/10/2015
Last Updated 12/15/2015
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC