Version Found: 2015.3
For designs that either use the TX_BITSLICE or RXTX_BITSLICE, the current High Speed SelectIO Wizard does not support the INIT setting for the bit slice which can cause problems if the initial state of the TX_BITSLICE must be high.
This does not affect RX only designs.
Note: this Answer Record should not be viewed in isolation. For all other known issues, and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
Within the TX_BITSLICE, the INIT attribute will determine the initial value of the TX_BITSLICEs serialized output port, O.
The simplest way to address this is to use XDC constraints to override the INIT values.
For example, in an example design from the High Speed SelectIO wizard design, the following command will set BS high.
While this is the simplest to implement, the problem is that the behavioral simulation will not reflect these types of constraints. To address behavioral simulation, you will need to edit the HDL.
First, a new parameter should be added within tx_bs.v with the instantiation using the newly defined parameter, C_TX_BITSLICE_INIT.
Please see the following example:
Add the 52 bit parameter C_TX_BITSLICE_INIT and connect to the TX_BITSLICE instantiation:
And in in the TX_BITSLICE instantiation add the attribute for INIT:
This allows the C_TX_BITSLICE_INIT parameter to be set within instantiation.
This parameter will need to be pulled up to a higher level for designs that have more than a single instantiation of the High Speed SelectIO wizard core.
Defining the C_TX_BITSLICE_INIT parameter and connecting the property within the hierarchy blocks will similarly be required in tx_bs.v, hssio_wiz_top.v.
Declare the parameter as follows:
And in the instantiation:
The following Answer Record can be consulted when modifying an IP: (Xilinx Answer 57546)
If needed, the edited IP can be packaged up and re-used. For more information see (UG1118).