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AR# 66219

Zynq Ultrascale+ MPSoC Processing System IP - Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode

Description

In the booting sequence the CSU Boot ROM does the configuration of "processor block level software controlled reset registers" to bring the processors out of resets.

In JTAG mode CSU Boot ROM doesn't get executed before the fsbl, hence manual steps are required to take the processors out of reset.

Solution

In JTAG mode, perform steps mentioned below to get the processors out of reset.


fpga -f .<project_path>/project_1.runs/impl_1/design_1_wrapper.bit
targets -set -filter {name =~ "PSU"}
mask_write 0XFFD80118 0x00800000 0x00800000
mask_write 0XFFD80120 0x00800000 0x00800000
# write bootloop and release A53-0 reset
mwr 0xffff0000 0x14000000
#E in below command brings only A53_0 out of reset.
mwr 0xFD1A0104 0x380E
targets -set -filter {name =~ "Cortex-A53 #0"}
stop
dow ./project_1.sdk/fsbl/Debug/fsbl.elf
con
stop

Expected to be fixed in 2016.1

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66219
Date Created 12/11/2015
Last Updated 12/15/2015
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
IP
  • Zynq UltraScale+ MPSoC Processing System