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While using PS + PL designs, no dedicated reset signal is available to reset PL from PS. This answer record documents the work-around for this issue.
Use any of the pins from GPIO as a reset pin with software toggle. Alternatively, use fabric PLL lock signal as reset.
Additionally, while using xsdb as a debugger, please use following set of commands to toggle the GPIO to assert and de-assert reset
This issue is expected to be fixed in the 2016.1 release.
Answer Number | Answer Title | Version Found | Version Resolved |
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66183 | Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues | N/A | N/A |
AR# 66220 | |
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Date | 12/29/2015 |
Status | Active |
Type | General Article |
Devices |
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Tools |
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IP |
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