Use of the "Use separate clock for RD/WR" feature in IPI when using connection automation might not work correctly .
There is no Xilinx IP which supports two clocks on a single interface. Our interconnect does not support this either. However, the PS architecture and AMBA specifications do have provision for this.
The downside is that the connection automation connects the AXI interface as a regular AXI Interface and connects one of the two clocks. This can lead to incorrect systems being generated by novice users.
To work around this issue, disable "Use Separate Clock For RD/WR" in PCW.