I receive the following error when trying to simulate the FIFO Generator v13.0 IP. It occurs when parsing the design file "fifo_generator_v13_0_rfs.vhd".
This error can occur in the following scenarios:
1. No pre-compiled libraries. FIFO Generator v13.0 is the first version that does not have Verilog behavior simulation model.
In VHDL, there is no option to dynamically load a library in the form of -y/-v like in Verilog.
You will need to compile Xilinx simulation libraries using compile_simlib.
2. The -kdb switch is used in the vhdlan command in VCS 2015.09. This error occurs when you want to compile an encrypted IP with -kdb.
It errors out in VCS 2015.09 only, VCS-MX J-2014.12 works fine.
You can work around the problem by not using the -kdb switch or by using an alternative version of VCS.
Note: -kdb is a non-default switch for compilation of our IP.
To avoid any adverse effects, Xilinx recommends that you pass default switches to IP source compilation.