In order to ensure that all RX Bitslices start aligned, the RX CLK should be stopped until the RX VTC_RDY signal is asserted. After this, the RXCLK can be started, however it must be started cleanly.
If the RX CLK is toggling during the RX RST or is not clean when it starts after an RX RST, then Bit slipping and channel / word alignment are required on the RX side to ensure alignment across the interface.
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
There are 2 clocking setup options for the RX interface, EDGE / CENTRE DDR and EDGE / CENTRE Strobe / Clock.
When EDGE or CENTRE DDR is selected then the RXPLL is sourced from the RXCLK:
More information can be found in XAPP1208: https://www.xilinx.com/support/documentation/application_notes/xapp1208-bitslip-logic.pdf
Similarly, when ASYNC is selected the same clock is used for the RX PLL and RX CLK (though connected differently) and the RX PLL cannot be stopped. Therefore the user will need to Bitslip and Channel Align the interface.
When EDGE or CENTRE Strobe / Clock is selected, the RX PLL is sourced from a separate clock on the RX side: