UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 66244

UltraScale - Source Synchronous interfaces - RX - Requirement to have the RX CLK stopped until the RX VTC_RDY is asserted

Description

In order to ensure that all RX Bitslices start aligned, the RX CLK should be stopped until the RX VTC_RDY signal is asserted. After this, the RXCLK can be started, however it must be started cleanly.

If the RX CLK is toggling during the RX RST or is not clean when it starts after an RX RST, then Bit slipping and channel / word alignment are required on the RX side to ensure alignment across the interface.

Note: this Answer Record should not be viewed in isolation.

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

There are two clocking setup options for the RX interface, EDGE / CENTRE DDR and EDGE / CENTRE Strobe / Clock.

When EDGE or CENTRE DDR is selected then the RXPLL is sourced from the Receive/Capture CLK:



This setup means that the Receive/Capture CLK needs to be active for the RX RST to complete and so the user will need to Bitslip and Channel Align the interface.

More information can be found in XAPP1208:

https://www.xilinx.com/support/documentation/application_notes/xapp1208-bitslip-logic.pdf


Similarly, when ASYNC is selected, the same clock is used for the RX PLL and Receive/Capture CLK (though connected differently) and the RX PLL cannot be stopped.

Therefore the user will need to Bitslip and Channel Align the interface.


When EDGE or CENTRE Strobe / Clock is selected, the RX PLL is sourced from a separate Receive/Capture clock on the RX side:



With this setup, you can stop the Receive/Capture clock while the RX side comes out of RST (signified by VTC_RDY asserting) and if the Receive/Capture CLK starts stable then no Bit Slipping or Channel alignment should be required.


Note: If you are using VARIABLE or VAR_LOAD mode, the RX_CLK port on the High Speed SelectIO Wizard is only used for updating the RX delay line, it is not the Receive/Capture CLK.

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 66244
Date 08/02/2017
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale