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AR# 66244

UltraScale - Source Synchronous interfaces - RX - Requirement to have the RX CLK stopped until the RX VTC_RDY is asserted


In order to ensure that all RX Bitslices start aligned, the RX CLK should be stopped until the RX VTC_RDY signal is asserted. After this the RXCLK can be started, however it must be started cleanly. 

If the RX CLK is toggling during the RX RST or is not clean when it starts after an RX RST, then Bit slipping and channel / word alignment are required on the RX side to ensure alignment across the interface.

Note: this Answer Record should not be viewed in isolation.

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)


There are 2 clocking set-up options for the RX interface, EDGE / CENTRE DDR and EDGE / CENTRE Strobe / Clock.

When EDGE or CENTRE DDR is selected then the RXPLL is sourced from the RXCLK:

This set-up means that the RX CLK needs to be active for the RX RST to complete and so the user will need to Bitslip and Channel Align the interface.

More information can be found in XAPP1208:


When EDGE or CENTRE Strobe / Clock is selected, the RX PLL is sourced from a separate clock on the RX side:

With this set-up you can stop the RXCLK while the RX side comes out of RST (signified by VTC_RDY asserting) and if the RXCLK starts stable then no Bit Slipping or Channel alignment should be required.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 66244
Date 04/18/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale