There is a known issue in Vivado 2015.4 and earlier revisions where spurious messages occur indicating a connectivity issue involving the BITSLICE_CONTROL to BITSLICE interface.
These are dedicated connections between the BITSLICE_CONTROL primitive and BITSLICE primitives (RXTX_BITSLICE, TX_BITSLICE, RX_BITSLICE).
For connections between the BITSLICE_CONTROL and the BITSLICE, the primitives were given a bus width of 40 [39:0].
However, the actual number of pins that need to be physically connected in the bus is fewer than 40. It is still required that all 40 pins be connected in the netlist. This problem is scheduled to be fixed in Vivado 2016.1.
For UltraScale Devices, the actual required physical connections are as follows, along with the connect nets that can be ignored for the RTSTAT-10 DRC:
|Driver||Receiver||Nets that can be ignored for RTSTAT-10 |
(with respect to BITSLICE_CONTROL pin)
|BITSLICE_CONTROL TX_BIT_CTRL_OUTx[26:0]||BITSLICE TX_BIT_CTRL_IN[26:0]||TX_BIT_CTRL_OUTx[39:27]|
|BITSLICE_CONTROL RX_BIT_CTRL_OUTx[21:0]||BITSLICE RX_BIT_CTRL_IN[21:0]||TX_BIT_CTRL_OUTx[39:22]|
|BITSLICE TX_BIT_CTRL_OUT[29:0]||BITSLICE_CONTROL TX_BIT_CTRL_INx[29:0]||TX_BIT_CTRL_INx[39:30]|
|BITSLICE RX_BIT_CTRL_OUT[32:0]||BITSLICE_CONTROL RX_BIT_CTRL_INx[32:0]||RX_BIT_CTRL_INx[39:33]|