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AR# 66278

Zynq UltraScale+ MPSoc, Vivado 2015.4 - SDK/XSDB debugger unable to read/write PL peripherals: "PL AXI slave ports access is not allowed"

Description

I have a simple MPSoC project with a BRAM in the PL. However, if I try do a memory read in XSDB (mrd), I get an error stating the following:

PL AXI slave ports access is not allowed

How can this be addressed?

Solution

Currently, the PL address ranges are not exported to the debugger as an allowable region to access.

The -force switch needs to be used to access the unknown range.

For example:

mrd -force 0x80000000

This issue is currently planned to be fixed starting in Vivado 2016.1.

AR# 66278
Date Created 12/18/2015
Last Updated 12/21/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.4.1