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AR# 66295

Zynq UltraScale+ MPSoC Processing System IP - PS-PL AXI Interfaces do not function correctly at 64-bit or 32-bit widths (or 128-bits for M_AXI_HP0_LPD)

Description

When using an AXI interface with 32 or 64-bit width (or 128-bits for M_AXI_HP0_LPD), the data is not arranged correctly, causing data corruption.

How do I resolve this?

Solution

Although the IP Integrator interface section is parameterized correctly, the PS registers which control the width are not updated in psu_init.tcl/.c, which is used by the debugger and FSBL.

To work around this issue, manually access the register and configure the AXI width before allowing AXI interface.

There are two issues in the current version of PCW:

  1. PS-PL AXI interface width settings are not correctly reflecting in psu_init. RDCTRL and WRCTRL registers for read and write channels should be written as per the AFI width configuration in PCW.
  2. The register writes for PS-PL AXI interface related settings are done before the AFI module is released from reset, so these settings have no effect. These settings should be done after AFI is released from reset.


To work around this issue, manually add the AXI width register setting to psu_ps_pl_isolation_removal_data() proc in psu_init, as these settings are used only when there is logic in the PL. Nothing needs to done for the AFI module reset because it has been released from reset prior to this step.

The relevant registers to be modified are:

AXI Interface
Register NameAddressBits
M_AXI_HPM0_FPDFPD_SLCR.axi_fs.dw_ss0_sel0xFD6150009:8
M_AXI_HPM1_FPDFPD_SLCR.axi_fs.dw_ss1_sel0xFD61500011:10
M_AXI_HPM0_LPDLPD_SLCR.axi_fs.dw_ss2_sel0xFF4190009:8
S_AXI_HPC0_FPDAFIFM0.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM0.AFIFM_WRCTRL.FABRIC_WIDTH0xFD360000 and 0xFD3600141:0
S_AXI_HPC1_FPDAFIFM1.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM1.AFIFM_WRCTRL.FABRIC_WIDTH0xFD370000 and 0xFD3700141:0
S_AXI_HP0_FPDAFIFM2.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM2.AFIFM_WRCTRL.FABRIC_WIDTH0xFD380000 and 0xFD3800141:0
S_AXI_HP1_FPDAFIFM3.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM3.AFIFM_WRCTRL.FABRIC_WIDTH0xFD390000 and 0xFD3900141:0
S_AXI_HP2_FPDAFIFM4.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM4.AFIFM_WRCTRL.FABRIC_WIDTH0xFD3A0000 and 0xFD3A00141:0
S_AXI_HP3_FPDAFIFM5.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM5.AFIFM_WRCTRL.FABRIC_WIDTH0xFD3B0000 and 0xFD3B00141:0
S_AXI_LPDAFIFM6.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM6.AFIFM_WRCTRL.FABRIC_WIDTH0xFF9B0000 and 0xFF9B00141:0


Register Values:

FPD_SLCR registers:

  • 2'b00 : 32-bit enabled
  • 2'b01 : 64-bit enabled
  • 2'b10 : 128-bit enabled
  • 2'b11 : Reserved

AXIFM registers:

  • 2'b11 : Reserved
  • 2'b10 : 32-bit Fabric
  • 2'b01 : 64-bit enabled
  • 2'b00 : 128-bit enabled

This issue is planned to be fixed in Vivado 2016.3 and later versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66295
Date Created 12/18/2015
Last Updated 09/28/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1
IP
  • Zynq UltraScale+ MPSoC Processing System