Congestion can be challenging to understand, due to the complexity of larger designs.
This article covers methodology and tools for overcoming congestion in Vivado designs.
Messaging - Messaging within route_design should indicate when there are high levels of congestion within the design. Below is an example:
In this case, the messaging indicates a congestion level of 5 (2^5) or a 32x32 area of tiles that have over 100 percent routing resources used. Higher than Level 4 can generally be a problem.
Metrics - From an open routed design, the Congestion Metrics (right-click within Device view -> Metric Vertical/Horizontal routing congestion per CLB) can show you the location of the congestion. When the metrics view is brought up, the "Metric Results will show the congestion percentage (%) and the tile in question. A value over 100 would mean that over 100 percent of the routing resources in this tile are used, and the router will have to divert routes that would normally use this tile around this area.
Utilization - One of the main reasons for congestion is the utilization of a design. Designs that have high utilization will be more susceptible to congestion. Generally, a design that is over 80% utilized (Slice LUTs) will become very difficult to route and meet timing. The actual percentage where this difficulty is seen is highly design dependent, and is affected by the number of control sets (clock, reset, and enable) in the design. Also, over-utilization of other site types such as FFs, LUTRAMs, block RAMs, and DSP sites can also lead to congestion. One suggestion to overcome such congestion would be to balance the utilization of different types of sites. For instance, if many LUTRAMs are causing an over-utilization of LUTs, then moving some of these to Block RAM sites could help. Please review the Control Signals and Control Sets section of the Vivado UltraFast Design Methodology Guide (UG949) for guidance suggested utilization and control set levels.
report_high_fanout_nets - Finding high fanout nets can be crucial in fighting congestion. Specifically non-clock control signals that have a high fanout can cause congestion. You can make a list of high fanout nets with synchronous drivers and use the "phys_opt_design -force_replication_on_nets" command to relieve congested areas. If a high fanout net is driven from a LUT and cannot be replicated with phys_opt_design, then this can either be manually replicated in the RTL, or a global buffer (BUFG) can be added if the added delay is acceptable.
report_design_analysis - The report_design_analysis -complexity command can also be used to see if a design is more complex and susceptible to congestion. report_design_analysis -help gives additional information on how to use this. From the IDE, navigate to Tools -> Report -> Report Design Analysis. Example command: "report_design_analysis -congestion -complexity -hierarchical_depth 10" which will analyze the complexity "Rent" and specify this for 10 hierarchical levels. The -congestion option will also list the most heavily utilized routing tiles.
Logic related to Congestion - Find the logic that occupies the congested tiles by building a schematic. This logic can be checked for connecting high-fanout nets directly related to this congestion. See (Xilinx Answer 66698) for more on this process.
Local vs Global Congestion - Congestion can be local to a certain region of the device, even when the overall device utilization is low. In this case, certain restrictions such as I/O connections or area constraints such as pblocks can cause the congestion and should be checked. Try loosening or removing pblock constraints to see how the results differ.
Check the Clock Placer Floorplan - Check the report_clock_utilization report for clocking floorplans that do not use enough resources for a specific clock. To do this, make a note of all the global clocks entering the clock region with congestion. Are there clocks that use too few clock regions? The placer might not be allocating enough clock regions for a specific clock. To work around this, you can edit the current clock floorplan to add another clock region which could alleviate the congestion. See (Xilinx Answer 66386) for more details on this.
Methods for reducing congestion:
Strategies & directives
Reducing Local Congestion
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