Version Found: v2.7 (Rev1)
Version Resolved and other Known Issues: See (Xilinx Answer 54646)
When the above configuration is selected, the core operates at a 62.5MHz AXI_ACLK frequency instead of 125Mhz which is the desired clock frequency.
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express
The tactical patch provided with this answer record allows you to operate at a 125MHz AXI_CLK frequency for the above configuration of the core. This will be fixed in a future release of the core.
To resolve the issue, install the patch attached to this answer record as described below.
After the patch is installed, the version of the AXI Memory Mapped to PCI Express core should indicate: v2.7 (Rev. 66348).
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
01/06/2016 - Initial release
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