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AR# 66348

AXI Memory Mapped to PCI Express v2.7 (Rev1) (Vivado 2015.4) - Zynq -1 Speed Grade - AXI Interface Clock Frequency too slow for x2Gen2 Configuration in Zynq -1 devices

Description

Version Found: v2.7 (Rev1)

Version Resolved and other Known Issues: See (Xilinx Answer 54646)


  • Core: AXI PCIe v2.7 (Rev1) core
  • Device: Zynq -1 or -1I or -1Q or -1L Speed Grade
  • Lane Width: x2
  • Link Speed: Gen2

When the above configuration is selected, the core operates at a 62.5MHz AXI_ACLK frequency instead of 125Mhz which is the desired clock frequency.


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This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express

Solution

The tactical patch provided with this answer record allows you to operate at a 125MHz AXI_CLK frequency for the above configuration of the core. This will be fixed in a future release of the core.

To resolve the issue, install the patch attached to this answer record as described below.

  • The provided patch is for Vivado 2015.4.x for the AXI Memory Mapped to PCI Express core.
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2015.4.x and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Add Repositories and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the AXI Memory Mapped to PCI Express core should indicate: v2.7 (Rev. 66348).

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

01/06/2016 - Initial release

Attachments

Associated Attachments

Name File Size File Type
AR66348_Vivado_2015_4_preliminary_rev1.zip 1 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54646 AXI Bridge for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 66348
Date Created 01/06/2016
Last Updated 01/20/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.4.1
IP
  • AXI PCI Express (PCIe)