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AR# 66360

UltraScale/UltraScale+ Memory IP - Core Container does not include *.csv file when a custom memory part is created

Description

Version Found: DDR4 v1.0, DDR3 v1.0, RLDRAM3 v1.0, QDRII+ v1.0

Version Resolved: See (Xilinx Answer 58435)

The IP Core Container does not archive and maintain the *.csv file required when creating and using a custom memory part for the UltraScale Memory IP (i.e. DDR4, DDR3, RLDRAM3, QDRII+ etc.). 

If the IP Core Container is used with a custom memory part in the memory IP, an error will occur complaining about the missing custom part definition.

Solution

To resolve this issue, avoid using the IP Core Container for any memory IP that has a custom memory part, or manually add the missing *.csv back into the Vivado project.

Revision History:

01/08/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 66360
Date 01/11/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
Tools
  • Vivado Design Suite - 2015.3
IP
  • MIG UltraScale
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