We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66386

Vivado - How to manually adjust a place_design clock floorplan


In some situations, it might be necessary to manually change a place_design clocking floorplan. This article describes how to do this.


The current floorplan for a design that has already been placed can be found by using the report_clock_utilization command. 

The "-write_xdc" option will also be needed in order to save the constraints to an XDC file. 

For example:

report_clock_utilization -write_xdc floorplan.xdc

The floorplan.xdc file can then be edited. A specific example of this would be to add a clock region that the original floorplan did not use, as shown below. 

After making the edits to the constraints file, it can be added as a constraints source, and implementation can be rerun. 

Note that the pblock will be viewable from an open implemented design, as this pblock is now a user defined pblock, and not a placer generated one.


AR# 66386
Date Created 01/12/2016
Last Updated 04/04/2016
Status Active
Type General Article
  • Vivado Design Suite