I have a Block Design (BD) which contains a Video Processing Subsystem (VPSS) IP core.
When I generate the output targets for the BD, not all of the HDL files for the Video Scaler (sub-core of the VPSS IP core) are generated if I choose the "Out of context per IP" option.
I do not see any error or warning about this during generation, but the synthesis step gives an error stating that the bd_0_v_vscaler_0_synth_1 is Out-of-date "Due to bd_0_v_vscaler_0_synth_1 - IP modified"
Going through the folder structure, I only see the top Verilog file generated, but the underlying Verilog files it needs do not exist.
Reading the runme.log from the .\project_1.runs\bd_0_v_vscaler_0_synth_1 folder give additional information about files not found and reports the following errors:
This problem has been seen under the following conditions:
Resetting the generated output products and then re-generating the BD resolves the problem.
This issue will be fixed in Vivado 2016.1.