UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66403

2015.4 Vivado IP Flows - Video Processing Subsystem IP core in a Block Design does not fully generate the first time

Description

I have a Block Design (BD) which contains a Video Processing Subsystem (VPSS) IP core.

When I generate the output targets for the BD, not all of the HDL files for the Video Scaler (sub-core of the VPSS IP core) are generated if I choose the "Out of context per IP" option.

I do not see any error or warning about this during generation, but the synthesis step gives an error stating that the bd_0_v_vscaler_0_synth_1 is Out-of-date "Due to bd_0_v_vscaler_0_synth_1 - IP modified"

Going through the folder structure, I only see the top Verilog file generated, but the underlying Verilog files it needs do not exist.

Reading the runme.log from the .\project_1.runs\bd_0_v_vscaler_0_synth_1 folder give additional information about files not found and reports the following errors:

ERROR: [Synth 8-439] module 'bd_0_v_vscaler_0_v_vscaler' not found [c:/test/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_v_proc_ss_0_0/bd_0/ip/ip_2/synth/bd_0_v_vscaler_0.v:178]
    Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32'sb00000000000000000000000000001100
    Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32'sb00000000000000000000000000100000
ERROR: [Synth 8-285] failed synthesizing module 'bd_0_v_vscaler_0' [c:/test/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_v_proc_ss_0_0/bd_0/ip/ip_2/synth/bd_0_v_vscaler_0.v:57]

Solution

This problem has been seen under the following conditions:

  • Running on a Windows operations systems
  • Generating the outputs for a Block Design containing Video Processing Subsystem (VPSS) IP core
  • User chooses the "Out of context per IP" option when generating
  • Two or more jobs are selected for runs.

Resetting the generated output products and then re-generating the BD resolves the problem.

This issue will be fixed in Vivado 2016.1.

AR# 66403
Date Created 01/14/2016
Last Updated 01/21/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.4