We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66434

High Speed SelectIO Wizard - Transmit interfaces may have TX_BITSLICE[0] out of alignment within each nibble


Version Found: 2015.3

For a transmit (TX) interface, one of the Bitslices can go out of alignment when TX_DELAY_FORMAT = TIME and TX_DELAY_VALUE = 0.

Bitslice[0] for each nibble can be affected by this issue. When looking at the entire byte group, this will mean that Bitslice[0] and Bitslice[6] could be affected.

BISC is only designed to be run when RX_DELAY_FORMAT = TX_DELAY_FORMAT.

When using the TX_DELAY_FORMAT only, there is a conflict with the default settings for RX_DELAY_FORMAT and as a result the BISC will not issue the required resets to align all of the bits.

Note: this Answer Record should not be viewed in isolation.

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)


There are two solutions that can be used to force the transmit interface into alignment.

Solution 1:

Set the TX_DELAY_VALUE to 1 or higher while keeping TX_DELAY_TYPE = TIME.

When any delay value is given, BISC will force the transmitter into alignment. By giving a non-zero value, BISC forces the alignment for the TX_BITSLICEs.

Solution 2:

Use the RXTX_BITSLICE where the RX_DELAY_TYPE and TX_DELAY_TYPE are both accessible.

Ensure that the RX_DELAY_FORMAT & TX_DELAY_FORMAT are both set to TIME.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 66434
Date 03/03/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
Page Bookmarked