UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66435

LogiCORE IP Video Processing Subsystem v1.0 - Clarification of color space mappings

Description

The product guide for the Video Processing Subsystem (PG231 from November 18, 2015) is not clear on some of the color mappings.

Particularly, Tables 2-5, 2-6, and 2-7.

Solution

Regarding Table 2-5 (Dual Pixels per Clock, 10 Bits per Component Mappint for YUV 4:2:2), 4:2:2 has 2 channels.

One channel carries Y and the second channel carries U and V interleaved in time, starting with U every line.

So when you do this for 2 pixels per clock, the mapping is as follows:

59:50 49:40 39:30 29:20 19:10 9:0
Zero padding
Zero padding V0 Y1 U0 Y0

4:2:0 adds vertical subsampling to 4:2:2 which is implemented in the AXI4 Stream by simply omitting the Chroma data on every other line. 

For example, for the first line in the frame (i.e. line 0 which is even) is mapped:


59:50 49:40 39:30 29:20 19:10 9:0
Zero padding
Zero padding V0 Y1 U0 Y0

Now, because the odd lines do not contain a valid Chroma component, they look like this:


59:50 49:40 39:30 29:20 19:10 9:0
Zero padding
Zero padding XXXX Y1 XXXX Y0

Linked Answer Records

Master Answer Records

AR# 66435
Date Created 01/19/2016
Last Updated 01/21/2016
Status Active
Type General Article
IP
  • Video Scaler