(Xilinx Answer 65199) covers Reference Clock Propagation Delay in 7 Series devices. Is similar behavior seen in UltraScale devices?
The reference clock takes time to propagate to the GTs PLL during FPGA configuration. The reference clock AC coupling capacitor also begins to charge up during configuration. Depending on the configuration method, the capacitor can still be charging after configuration DONE.
In the event that the GTH/GTY transceivers are released from reset before the reference clock has settled through the RC circuit, a second reset of the transceiver (C/QPLL+TX/RX) after the reference clock has settled might be necessary.
The max wait time for the reference clock to settle in UltraScale would be less than the 3ms mentioned for 7 series as the AC coupling capacitor recommended for UltraScale is 10nF.