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AR# 66493

LogiCORE IP AXI Video Direct Memory Access v6.2 - How to get an interrupt at the end of the frame?

Description

I am trying to use the AXI VDMA and I need to get an interrupt at the end of each frame.

This is to let me know that the transfer to/from memory is complete so that my processor can go and access that memory without fear of stomping on the same buffer that the VDMA is using. 

How can I accomplish this?

Solution

If you are using the MM2S interrupt, the recommended flow is that you use free-run mode. In free-run mode, the core will generate an interrupt when the internal line/frame counters reach the programmed frame size. 

In other words, it will assert at the end of the frame before the next vertical blanking period. If you also need external synchronization to control when the VDMA starts to pull a new frame from memory, you should use an external Fsync into the VTC as described in the (PG044) section  'Master Mode with Fsync'.

If you are using the S2MM interrupt, free-run mode can be problematic unless you can guarantee you will never have partial frames or frame size changes from hot-plug events, etc. As a result, it is usually not recommended. As such, it is most common to use either 'External Fsync' or 'Fsync on TUSER.' 

When the VDMA is configured in either of these two modes, it will instead issue its interrupt on an fsync event (i.e. falling edge of Fsync or tuser). So instead of issuing an interrupt when the frame completes (before vertical blanking), the interrupt asserts at the first active pixel of the next frame. This can be problematic for some use cases.

In such cases, it is possible to track when the write (or read) channels have received (or transferred) the required number of lines. This information is available in the test vector bits which should be enabled with the following Tcl command:

set_property -dict [list CONFIG. C_ENABLE_DEBUG_INFO_4 {1}] [get_bd_cells axi_vdma_inst_name]

This will enable a signal called axi_vdma_tstvec. The relevant bits are:

  • axi_vdma_tstvec[32] - This signal is asserted when the write (S2MM) channel has received the programmed number of video lines (tlast) at the streaming interface. It is cleared when the next frame processing starts (i.e. the next fsync event). The reset value is 1.
  • axi_vdma_tstvec[1] - This signal is asserted when the read (MM2S) channel has transferred the programmed number of video lines at the streaming interface. It is cleared when the next frame processing starts (i.e. the next fsync event). The reset value is 1.

Therefore, you could use the rising edge of these signals to trigger an interrupt (though software should check to make sure that no frame size errors occurred first).

Note that the S2MM side tracks tlast pulses. So axi_vdma_tstvec[32] will actually assert slightly before the last line finally makes it to backing memory.

AR# 66493
Date Created 01/27/2016
Last Updated 02/01/2016
Status Active
Type General Article
IP
  • AXI Video Direct Memory Access
  • AXI Video DMA
  • AXI Video DMA