When using Bitslice  of a nibble for a normal GPIO input with a mixture of Component or Native mode delays in the same nibble, the pin will not be active / available during calibration.
Once DLY_RDY is asserted, the pin will be active.
Note: this Answer Record should not be viewed in isolation.
For all other known issues with component mode, please refer to (Xilinx Answer 66012).
Bitslice 0 is used for delay calibration. During the calibration, the I/O is not available, it only becomes available after DLY_RDY asserts.
This happens whenever a Delay that needs calibration is located in the nibble in either Component or Native mode. It does not matter whether the I/O at BITSLICE0 uses a delay or not.
The I/O pin is not available and might not have the desired value. A high input can be read as low.
At power-up, if the IDELAYCTRL does not have a clock, then the blockage could persist until the clock is supplied and the RDY finally asserts.
The DRC error for this condition was added in the 2016.1 release.
There is one exception that is documented in (UG571): In an I/O bank, there is one differential QBC/GC pin set, or two single-ended QBC/GC pins.
Those can be used to carry a clock to a BUFG, MMCM or PLL while BISC is running and while the possibly connected BITSLICE_0 is unavailable.
The DRC will not flag for this exception.