Vivado versions prior to 2016.1 are configured with a stronger drive than expected for HSTL_12, DIFF_HSUL_12_DCI and HSUL_12_DCI
In Vivado versions prior to 2016.1, HSUL drivers default to an output impedance setting of RDRV_40_40.
In Version 2016.1 and beyond the settings will be RDRV_48_48.
For existing designs, the output impedance can be set to the RDRV_48_48 by opening a netlist design and selecting the pin planning view in the GUI.
Alternatively this can be set in the XDC file: