UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6655

FPGA Express - How do I do operator overloading in FPGA Express?

Description


General Description:

If I have two packages that have the same operator, how do I

chose which package the operator comes from? For example, the

Synopsys packages std_logic_signed and std_logic_unsiged both

have the "=" defined. If both packages are needed in the design,

which operator gets chosen?

Solution


To reolve this, the operator has to be declared as:



library.package_name."operator"



So in some VHDL code, the function would look like:



result <= IEEE.std_logic_unsigned."="(in1,"0000");
AR# 6655
Date Created 08/31/2007
Last Updated 03/22/2011
Status Archive
Type General Article